This invention relates, inter alia, to clock and data recovery (“CDR”) circuitry, especially CDR circuitry that may be included on an integrated circuit (“IC”) device. Illustrative ICs that may employ the invention include programmable (or configurable) ICs such as programmable logic-devices (“PLDs”), field-programmable gate arrays (“FPGAs”), programmable microcontrollers, and the like.
An important block in transceiver circuitry is the CDR circuit that resides in the receiver portion of the transceiver. CDR is used to extract high-speed clock information and high-speed data information from a received high-speed serial data signal. For example, the transceiver may be on one IC in a larger system, and the high-speed serial data signal may be received by that IC from another IC in the system.
The CDR uses a reference clock signal at a particular frequency (having a known relationship to the nominal frequency, bit rate, or data rate of the high-speed serial data signal) to initially train its frequency. (Although the reference clock signal has a known frequency relationship to the high-speed serial data signal, there is typically no required phase relationship between these two signals.)
After the above initial frequency training, the CDR then uses the data stream (in the high-speed serial data signal) to frequency-and-phase align the CDR with the data. Such frequency and phase alignment allows the CDR to output a recovered clock signal having phase and frequency that are suitable for recovering (and possibly also further processing) data information from the high-speed serial data signal. (The recovered data may be contained in a so-called retimed data signal.)
CDR circuitry may be required for inclusion in relatively general-purpose devices. For example, ICs like PLDs, FPGAs, programmable microcontrollers, and the like may be designed for use in any of a wide range of applications. The manufacturer of the IC does not know all the specifics of all the uses to which various users of the IC may wish to put the IC in larger systems being built by such users. It is desirable for the IC manufacturer to be able to provide an IC product that can meet the requirements of a wide range of uses, because this increases sales volume of the IC (which can help to lower unit cost of the IC). In such contexts, it can be desirable for the CDR circuitry to be able to support any of many high-speed serial data communication (signalling) protocols, standards, or specifications. Each of these protocols requires the CDR to extract data and clock signal information from a data stream running at a particular frequency.
An example of a high-speed serial interface (“HSSI”) protocol that is fairly widely used is so-called Peripheral Component Interface Express (“PCIE”). There are three different PCIE standards: Gen1, Gen2, and Gen3. These standards require data running at 2.5 Gigabits per second (“Gbps”), 5.0 Gbps, and 8.0 Gbps, respectively. In general, PCIE can include so-called auto-speed negotiation among these three speed standards. This means that a transmitter may signal that it wishes to communicate at a particular one of these speeds, and the receiver must respond by switching to that speed (assuming that the receiver can operate at that speed). A desirable attribute of CDR circuitry (especially in general-purpose circuitry of the various kinds that are mentioned above) is the ability to support auto-speed negotiation such as is characteristic of PCIE. (Auto-speed negotiation is also sometimes referred to as auto-negotiation.) CDR circuitry is also desired that can operate at any frequency in a wide band of data rates (frequencies) in order to support any of a large number of different HSSI protocols.